Network Processors: Architectures, Protocols, and Platforms

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August 2003



Revolutionary network processors are already making sweeping changes in the network design field. Microchips optimized for high-speed communications, they impact everything from switching to security. These programmable chip sets are being rolled out with great fanfare by Intel, IBM, Motorola, Agere and others, but network designers and analysts know very little about them. This book is a very practical education in what these products look like under the hood and how to make the most of them.-- How NP architectures differ from CPUs (Central Processing Units)-- How to analyze protocols, platforms and market forces-- How to plan for a new generation of chips, routers and switches


<H2>PART 1: FUNDAMENTALS<H3>Chapter 1: The Evolution of Network Technology: Distributed Computing and the Convergence of Networks<H3>Chapter 2: Network Processors: Justification<H3>Chapter 3: Packet Processing<H2>PART 2: NETWORK PROCESSOR ARCHITECTURE<H3>Chapter 4: IBM PowerNP(tm)<H3>Chapter 5: Intel IXA(tm) Network Processors<H3>Chapter 6: AMCC nP(tm) Family of Network Processors<H3>Chapter 7: Agere PayloadPlus(r) Family of Network Processors<H3>Chapter 8: Motorola's C-Port(tm) Family of Network Processors<H3>Chapter 9: Other NPU Architectures<H3>Chapter 10: Alternative Approaches to Network Processing: Net ASICs and Designing with IP Cores<H2>PART 3: PERIPHERAL CHIPS SUPPORTING NETWORK PROCESSORS: STORAGE PROCESSORS, CLASSIFICATION PROCESSORS, SEARCH ENGINES, SWITCH FABRICS, AND TRAFFIC MANAGERS<H3>Chapter 11: Storage Network Processors (SNPs)<H3>Chapter 12: Search Engines<H3>Chapter 13: Classification Processors<H3>Chapter 14: Switch Fabrics<H3>Chapter 15: Traffic Managers<H2>PART 4: PUTTING EVERYTHING TOGETHER<H3>Chapter 16: Systems Engineering Issues<H2>PART 5: SECURITY COPROCESSORS<H3>Chapter 17: Security Coprocessors<H4>LIST OF ACRONYMS<H4>APPENDIX I: OVERVIEW OF NETWORK-PROCESSOR PRODUCTS AND PLATFORMS<H4>APPENDIX II: TYPICAL TRAFFIC LOAD (in Millions of Packets per Second) CORRESPONDENCE AT VARIOUS LINK SPEEDS AND PACKET SIZES<H4>APPENDIX III: STANDARDIZATION EFFORTS IN NETWORK PROCESSING<H4>INDEX


Panos C. Lekkas (Framingham MA) is a 20-year veteran of the communications chip industry, including a stint as the lead architect for IBM's PowerPC. Most recently, as founder and principal of TeleHubLink, he created a family of microchips for network security. Lekkas co-authored the bestselling book Wireless Security, contributing a unique section on hardware issues and solutions.
EAN: 9780071409865
ISBN: 0071409866
Untertitel: 'McGraw-Hill Network Engineerin'. Sprache: Englisch.
Erscheinungsdatum: August 2003
Seitenanzahl: 456 Seiten
Format: gebunden
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