Integrated Circuit Failure Analysis: A Guide to Preparation Techniques
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BeschreibungFault analysis of highly-integrated semiconductor circuits has become an indispensable discipline in the optimization of product quality. Integrated Circuit Failure Analysis describes state-of-the-art procedures for exposing suspected failure sites in semiconductor devices. The author adopts a hands-on problem-oriented approach, founded on many years of practical experience, complemented by the explanation of basic theoretical principles. Features include: Advanced methods in device preparation and technical procedures for package inspection and semiconductor reliability. Illustration of chip isolation and step-by-step delayering of chips by wet chemical and modern plasma dry etching techniques. Particular analysis of bipolar and MOS circuits, although techniques are equally relevant to other semiconductors. Advice on the choice of suitable laboratory equipment. Numerous photographs and drawings providing guidance for checking results. Focusing on modern techniques, this practical text will enable both academic and industrial researchers and IC designers to expand the range of analytical and preparative methods at their disposal and to adapt to the needs of new technologies.
InhaltsverzeichnisPurpose and Importance of Preparatory Semiconductor Analysis. Opening the Package: Chip Insulation. Wet Chemical Etching Procedures for Removing Layers of the Chip Structure. Crystallographic Etching in the Silicon. Dry Etching in the Plasma. Microsectioning Technology, Metallography. Outlook. Appendices. Index.
Untertitel: 'Quality and Reliability Engine'. New. Sprache: Englisch.
Verlag: JOHN WILEY & SONS INC
Erscheinungsdatum: Februar 1998
Seitenanzahl: 190 Seiten